| 发明名称 |
INTEGRATED CIRCUIT DEVICE WITH PROGRAMMABLE ANALOG SUBSYSTEM |
| 摘要 |
An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks. |
| 申请公布号 |
US2016065216(A1) |
申请公布日期 |
2016.03.03 |
| 申请号 |
US201514668984 |
申请日期 |
2015.03.26 |
| 申请人 |
Cypress Semiconductor Corporation |
发明人 |
Thiagarajan Eashwar;Kutz Harold M.;Klein Hans;Johal Jaskarn Singh;Vanitegem Jean-Paul;Castor-Perry Kendall V.;Hastings Mark E.;Richardson, JR. Amsby D.;Pai Maroor Anasuya;Khan Ata;Seguine Dennis R.;Byrkett Bruce E.;Liepold Carl Ferdinand;Van Antwerpen Hans |
| 分类号 |
H03K19/0175;H03M1/38;H03K19/003;H03K19/00 |
主分类号 |
H03K19/0175 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An integrated circuit (IC) device, comprising:
a plurality of analog blocks, including
at least one fixed function analog circuit, andat least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the plurality of analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; wherein the plurality of analog blocks is different from the plurality of I/Os; a digital section comprising digital circuits; a reconfigurable routing network configured to provide at least two different types of signal routing between any of the plurality of analog blocks, comprising a standard routing and at least one or more of a low resistance routing and a low noise routing; and a processor interface coupled to the plurality of analog blocks. |
| 地址 |
San Jose CA US |
