发明名称 SEMICONDUCTOR DEVICE
摘要 A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased.
申请公布号 US2016064383(A1) 申请公布日期 2016.03.03
申请号 US201514935607 申请日期 2015.11.09
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 KATO Kiyoshi;NAGATSUKA Shuhei;INOUE Hiroki;MATSUZAKI Takanori
分类号 H01L27/108 主分类号 H01L27/108
代理机构 代理人
主权项 1. A semiconductor device comprising: a plurality of memory cells each including a first transistor and a second transistor, the first transistor comprising:a first channel formation region;a first gate insulating layer provided over the first channel formation region;a first gate electrode provided over the first gate insulating layer, overlapping with the first channel formation region; anda first source electrode and a first drain electrode electrically connected to the first channel formation region,the second transistor comprising:a second channel formation region;a second source electrode and a second drain electrode electrically connected to the second channel formation region;a second gate electrode overlapping with the second channel formation region; anda second gate insulating layer provided between the second channel formation region and the second gate electrode, wherein the first transistor and the second transistor are provided so that at least parts of the first transistor and the second transistor overlap with each other, and wherein a wiring connecting one of the memory cells to another memory cell is electrically connected to one of the first source electrode and the first drain electrode through one of the second source electrode and the second drain electrode.
地址 Atsugi-shi JP