PARALLEL INTERFACE AND INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a parallel interface capable of equalizing delay amounts of a data signal and a clock signal even on a relatively long distance wiring, and an integrated circuit.SOLUTION: A parallel interface 1 includes: input parts IO (IO0-IO23) inputting predetermined data signals (D0-D23) and a clock signal (PCLK) in parallel; output parts (output lines B0-B23) synchronizing the predetermined data signals with the clock signal and outputting the predetermined data signals in parallel; and a plurality of transmission paths (first connection lines LA0-LA7, second connection lines LB0-LB7 and dummy wirings DM0-DM7) where the predetermined data signals and the clock signal are transmitted in parallel between the input parts and the output parts. The transmission paths comprise respective wiring patterns having electric lengths not equal to each other and capacitances electrically equal to each other.SELECTED DRAWING: Figure 2