PARAMETER MODELING FOR SEMICONDUCTOR ARRANGEMENTS

摘要

One or more systems and techniques for modeling are provided. An original device model, such as a SPICE model, is used as a basis for fabricating a semiconductor arrangement, such as an integrated circuit arrangement, upon a semiconductor wafer. Fabrication process variations cause measured e-parameters and measured size e-parameters of the semiconductor arrangement to vary from original design parameters of the original device model. Accordingly, a partial set of e-parameters and a partial set of size e-parameters are measured from the semiconductor arrangement, and are expanded into a full set of e-parameters and a full set of size e-parameters using e-parameter derivation and size-centric derivation. The original device model is retargeted using the full set of e-parameters and the full set of size e-parameters to create a new device model that more accurately represents the real-world or fabricated semiconductor arrangement.

主权项

1. A method for modeling, comprising:
obtaining a partial set of e-parameters measured from a semiconductor arrangement, the partial set of e-parameters comprising one or more measured e-parameters; performing e-parameter derivation to expand the partial set of e-parameters to a full set of e-parameters, the full set of e-parameters comprising one or more derived e-parameters; and retargeting an original device model for the semiconductor arrangement using the full set of e-parameters to create a new device model that models the semiconductor arrangement.