发明名称 Multilevel encoding and multistage decoding
摘要 Embodiments relate to multilevel encoding and multistage decoding concepts for reducing memory requirements at decoder side. Embodiments are particularly suited for LDPC block and/or LDPC convolutional component codes. The ideas of embodiments are threefold: Firstly, the decoder memory utilization may be decreased by the use of a special bit mapping that reduces the memory consumption of the egress memories. Further, ingress memories, which need to store complex values, may be reduced. This may be achieved by an optimization of the codes such that the decoding delays are minimized and/or by using hybrid schemes, where spatially coupled or convolutional LDPC codes are combined with LDPC block codes yielding an overall minimized memory usage.
申请公布号 EP2991231(A1) 申请公布日期 2016.03.02
申请号 EP20140183086 申请日期 2014.09.01
申请人 ALCATEL-LUCENT DEUTSCHLAND AG 发明人 SCHMALEN, LAURENT
分类号 H03M13/11;H03M13/25;H04L1/00 主分类号 H03M13/11
代理机构 代理人
主权项
地址