A display apparatus (110) includes gate lines (GL1, GL2 ...) configured to receive gate signals, data lines (DL1, DL2 ...) arranged to cross the gate lines and configured to receive data voltages, and pixels (PX) grouped into first pixel groups (PG1) and second pixel groups (PG2) and connected to the gate lines and the data lines. The gate signals are configured to be applied to the gate lines in a predetermined order while skipping at least one gate line without being sequentially and consecutively applied to two gate lines adjacent to each other among the gate lines.
