发明名称 Memory systems including nonvolatile buffering and methods of operating the same
摘要 A nonvolatile memory system can include a nonvolatile memory device that can be configured to store data and a nonvolatile memory buffer circuit that can be configured to store data of a type that is predetermined to be flushed to the nonvolatile memory device in a sudden power off backup operation of the nonvolatile memory system, whereas a volatile memory buffer circuit can be configured to store other data of a type that is not to be flushed to the nonvolatile memory device in the sudden power off backup operation of the nonvolatile memory system. A memory controller can be coupled to the nonvolatile memory device, the nonvolatile memory buffer circuit, and to the volatile memory buffer circuit, where the memory controller can be configured to store received data or processed data in the nonvolatile memory buffer circuit responsive to determining that the received data or processed data is of the type that is predetermined to be flushed to the nonvolatile memory device in the sudden power off backup operation of the nonvolatile memory system.
申请公布号 US9274983(B2) 申请公布日期 2016.03.01
申请号 US201414326898 申请日期 2014.07.09
申请人 Samsung Electronics Co., Ltd. 发明人 Park KwangSoo
分类号 G11C11/34;G06F13/16 主分类号 G11C11/34
代理机构 Myers Bigel Sibley & Sajovec, P.A. 代理人 Myers Bigel Sibley & Sajovec, P.A.
主权项 1. A nonvolatile memory system comprising: a nonvolatile memory device; a memory controller configured to receive data from an external device and/or from the nonvolatile memory device in response to a request from the external device to provide received data, the memory controller configured to determine an attribute of the received data or an attribute of processed data generated through processing of the received data, and configured to generate first and second memory selection signals based on the attribute of the received data determined by the memory controller; and a buffer circuit configured to temporarily store data under control of the memory controller, wherein the buffer circuit comprises: a first buffer memory configured to communicate with the memory controller through a buffer channel, the first buffer memory configured to temporarily store the received data or the processed data in response to the first memory selection signal and under control of the memory controller; and a second buffer memory configured to communicate with the memory controller through the buffer channel, the second buffer memory configured to temporarily store the received data and/or the processed data responsive to the second memory selection signal under control of the memory controller, and wherein the first buffer memory comprises a volatile random access memory and the second buffer memory comprises a nonvolatile random access memory.
地址 KR