发明名称 Conversion of a discrete-time quantized signal into a continuous-time, continuously variable signal
摘要 Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank.
申请公布号 US9276602(B1) 申请公布日期 2016.03.01
申请号 US201514697574 申请日期 2015.04.27
申请人 Syntropy Systems, LLC 发明人 Pagnanelli Christopher
分类号 H03M1/66;H03M1/74;H03M1/08 主分类号 H03M1/66
代理机构 Joseph G. Swan, P.C. 代理人 Joseph G. Swan, P.C.
主权项 1. An apparatus for converting a discrete-time quantized signal into a continuous-time, continuously variable signal, comprising: an input line for accepting full-rate samples of an input signal that are discrete in time and in value, that are separated in time by a full-rate sampling period, and that represent a signal sampled at a full-rate sampling frequency corresponding to the full-rate sampling period; a parallel signal processor having an input coupled to said input line and having a plurality of sub-rate outputs, each sub-rate output providing a different subsampling phase of a complete signal that is output by said apparatus; a first multi-bit-to-variable-level signal converter which is coupled to a first sub-rate output of the parallel signal processor and which operates at a sampling rate that is less than or equal to the full-rate sampling frequency of said input signal; a second multi-bit-to-variable-level signal converter which is coupled to a second sub-rate output of the parallel signal processor and which operates at the sampling rate; and a signal combiner coupled to an output of each of said first and second multi-bit-to-variable-level signal converters, wherein the outputs of said first and second multi-bit-to-variable-level signal converters are combined by the signal combiner, as continuous-time signals at the sampling rate of said first and second sub-rate outputs, using at least one summing operation, wherein at least one delay operation has been applied to at least one of said first sub-rate output and said second sub-rate output prior to said at least one summing operation, and wherein said at least one delay operation and said at least one summing operation together produce a filter response with a lowpass cutoff frequency that is: less than or equal to the full-rate sampling frequency of the input signal, and greater than or equal to a maximum frequency component of said input signal.
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