Semiconductor device including gate channel having adjusted threshold voltage

摘要

A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel.

主权项

1. A method of forming a semiconductor device, the method comprising:
forming at least one first semiconductor fin on an nFET portion of a semiconductor substrate, the at least one first semiconductor fin having an nFET channel region interposed between a pair of nFET source/drain regions; forming at least one second semiconductor fin on a pFET portion of the semiconductor substrate, the at least one second semiconductor fin having a pFET channel region interposed between a pair of pFET source/drain regions; forming a gate stack on the nFET channel region and the pFET channel region; forming an epitaxial liner on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel region, wherein the forming an epitaxial liner comprises: removing a dummy gate element from the gate stack formed on the pFET channel region to expose the pFET channel region of at least one second semiconductor fin; etching the exposed pFET channel region to form an etched pFET channel portion, the etched pFET channel portion having a first thickness that is less than a second thickness of the at least one first semiconductor fin; and epitaxial growing silicon germanium (SiGe) on the etched pFET channel portion, wherein a combination of the etched pFET channel portion and the epitaxial liner defines a third thickness that is equal to the second thickness of the at least one first semiconductor fin.