Processor and instruction processing method in processor

摘要

The present invention relates to a processor including: an instruction cache configured to store at least some of first instructions stored in an external memory and second instructions each including a plurality of micro instructions; a micro cache configured to store third instructions corresponding to the plurality of micro instructions included in the second instructions; and a core configured to read out the first and second instructions from the instruction cache and perform calculation, in which the core performs calculation by the first instructions from the instruction cache under a normal mode, and when the process enters a micro instruction mode, the core performs calculation by the third instructions corresponding to the plurality of micro instructions provided from the micro cache.

主权项

1. A processor, comprising:
an instruction cache configured to store at least a first instruction read from an external memory and a second instruction, the second instruction being dividable into a plurality of pieces, each piece being a micro instruction; a micro cache configured to store a plurality of third instructions corresponding to the plurality of micro instructions included in the second instruction; and a core configured to read out the first and second instructions from the instruction cache and perform calculation, wherein the core
performs the calculation using the first instruction from the instruction cache in a normal mode, andperforms the calculation using the plurality of third instructions corresponding to the plurality of micro instructions provided from the micro cache in a micro instruction mode.