Contact metallurgy for self-aligned high electron mobility transistor

摘要

A metallization scheme employing a first refractory metal barrier layer, a Group IIIA element layer, a second refractory metal barrier layer, and an oxidation-resistant metallic layer is employed to form a source region and a drain region that provide electrical contacts to a compound semiconductor material layer. The first and second refractory metal barrier layer are free of nitrogen, and thus, do not introduce additional nitrogen into the compound semiconductor layer, while allowing diffusion of the Group IIIA element to form locally doped regions underneath the source region and the drain region. Ohmic contacts may be formed at a temperature as low as about 500° C. This enables fabrication of FET whose source and drain are self-aligned to the gate.

主权项

1. A semiconductor structure comprising a high electron mobility transistor (HEMT), wherein said HEMT comprises:
a substrate including a stack of a substrate compound semiconductor layer and a top compound semiconductor layer; a gate stack including, from bottom to top, a gate electrode and a gate electrode contact structure, wherein said gate electrode is of unitary construction and comprises a lower vertical portion contacting a horizontal surface of a portion of said top compound semiconductor layer, a horizontal portion located on said lower vertical portion and extending beyond sidewalls of said lower vertical portion, and a first vertical arm portion and a second vertical arm portion extending upward from either end of said horizontal portion, said horizontal portion and said first and said second vertical arm portions defining a cavity, and wherein said gate contact structure is located over top surfaces of said first and said second vertical arm portions and sidewalls and a bottom of said cavity; a source region contacting a first portion of a top surface of said top compound semiconductor layer; and a drain region contacting a second portion of said top surface of said top compound semiconductor layer, wherein said second portion is laterally spaced from said first portion by a width of said horizontal portion of said gate electrode, and wherein each of said gate electrode contact structure, said source region, and said drain region comprises a vertical stack, from bottom to top, of a first refractory metal barrier layer, a Group IIIA element layer, a second refractory metal barrier layer, and an oxidation-resistant metallic layer; a source-side diffusion region located beneath said source region and comprising a first portion of said top compound semiconductor layer; and a drain-side diffusion region located beneath said drain region and comprising a second portion of said top compound semiconductor layer, wherein each of said first portion and said second portion of said to compound semiconductor layer is doped with said Group IIIA element from said Group IIIA element layer, and wherein said source-side diffusion region and said drain-side diffusion region are laterally spaced from each other by a fluorine-doped region located within said portion of said top compound semiconductor layer and underlying said horizontal surface.