Memory arrays for both good data retention and low power operation

摘要

Designs and programming schemes can be used to form memory arrays having low power, high density and good data retention. High resistance interconnect lines can be used to partition the memory array can be partitioned into areas of high data retention and areas of low data retention. Variable gate voltages can be used in control transistors to store memory values having different data retention characteristics.

主权项

1. A method for forming a memory array, the method comprising:
forming a first section of memory cells in the memory array,
wherein the first section has a first density of memory cells,wherein the first density of memory cells is configured to receive a first power and to have a first memory retention time;wherein the first section of memory cells is connected to an interconnect line using a first set of connectors; forming a second section of memory cells in the memory array,
wherein the second section of memory cells is connected to the interconnect line using a second set of connectors having a lower resistance than the first set of connectors;wherein the second section has a second density of memory cells,wherein the second density of memory cells is configured to receive a second power and to have a second memory retention time,wherein the first density is higher than the second density,wherein the first power is lower than the second power,wherein the first memory retention time is shorter than the second memory retention time, andwherein a memory value is stored in the first section or in the second section based on a retention time requirement of the memory value.