| 摘要 |
A system, method, and computer program product are provided for implementing asymmetric AES-CBC (Advanced Encryption Standard-Cipher Block Chaining) channels usage between encryption and decryption of data. In operation, data to be written to memory is identified. In addition, the data is encrypted utilizing a first AES-CBC channel. Additionally, at least one of a plurality of AES-CBC channels is utilized to decrypt the data to achieve a determined performance target. |
| 主权项 |
1. A method, comprising:
identifying, by a hardware processor of a system, data to be written to hardware memory of the system; encrypting, by the hardware processor, the data utilizing a first number of a plurality of AES-CBC channels of the system, to form encrypted data; storing, by the hardware processor, the encrypted data in the hardware memory; determining, by the hardware processor of the system, that the encrypted data is to be read from the hardware memory; determining, by the hardware processor, a second number of the plurality of AES-CBC channels of the system to utilize to decrypt the encrypted data, wherein the second number is different than the first number and achieves a determined performance target; while reading the encrypted data from the hardware memory, decrypting the encrypted data utilizing the determined second number of the plurality of AES-CBC channels to achieve the determined performance target; wherein the performance target is a speed for the decrypting that is determined as a function of a speed of the encrypting, such that the second number of the plurality of AES-CBC channels of the system to utilize to decrypt the encrypted data is determined as that which achieves the determined speed for the decrypting; wherein the speed determined for the decrypting is determined by multiplying a predefined integer by the speed of the encrypting, the predefined integer being greater than one. |
