| 主权项 |
1. A microprocessor that processes conditional non-branch instructions, wherein each conditional non-branch instruction specifies a condition, wherein each conditional non-branch instruction instructs the microprocessor to perform an operation if the condition is satisfied and to not perform the operation if the condition is not satisfied by condition flags of the microprocessor, the microprocessor comprising:
a predictor, configured to provide a prediction about a conditional non-branch instruction; an instruction translator, configured to:
translate the conditional non-branch instruction into a no-operation with condition code microinstruction when the prediction predicts the condition will not be satisfied, wherein the no-operation with condition code microinstruction performs no operation other than to enable an execution unit to scrutinize the prediction; andtranslate the conditional non-branch instruction into a single operational with condition code microinstruction to unconditionally perform the operation when the prediction predicts the condition will be satisfied and that enables an execution unit to scrutinize the prediction;wherein the instruction translator translates instructions of x86 instruction set architecture (ISA) programs and Advanced RISC Machines (ARM) ISA programs into microinstructions defined by a microinstruction set of the microprocessor, wherein the microinstructions are encoded in a distinct manner from the manner in which the instructions defined by the instruction sets of the x86 ISA and ARM ISA are encoded; and an execution pipeline, including an instruction issue unit and a plurality of execution units, wherein the instruction issue unit is operable to issue the single operational with conditional code microinstruction to a selected one of the plurality of execution units, and the selected execution unit is operable to execute the single operational with conditional code microinstruction. |
