Memory elements with stacked pull-up devices

摘要

Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may have an output serving as a second data storage node for the memory cell. Access transistors may be coupled between the first and second data storage nodes and corresponding data lines. Each of the first and second inverting circuit may have a pull-down transistor and at least two pull-up transistors stacked in series. The pull-down transistors may have body terminals that are reverse biased to help reduce leakage current through the first and second inverting circuits. The memory cell may be formed using a narrower two-gate configuration or a wider four-gate configuration.

主权项

1. An integrated circuit, comprising:
a data line; a plurality of bistable memory elements, wherein each bistable memory element in the plurality of bistable memory elements is coupled to the data line and includes at least one inverting circuit having a plurality of stacked pull-up transistors, wherein the stacked pull-up transistors in the at least one inverting circuit have gate terminals that are shorted to one another; and a dummy gate conductor that is interposed between two adjacent bistable memory elements in the plurality of bistable memory elements and that is electrically floating.