发明名称 |
Process for fabricating an integrated circuit having trench isolations with different depths |
摘要 |
A process for fabricating an integrated circuit includes, in a stack of layers including a silicon substrate overlaid with a buried insulating layer overlaid with a silicon layer, etching first trenches into the silicon substrate, depositing a silicon nitride layer on the silicon layer to fill the first trenches and form first trench isolations, forming a mask on the silicon nitride layer, etching second trenches into the silicon substrate, in a pattern defined by the mask, to a depth greater than a depth of the first trenches, filling the second trenches with an electrical insulator to form second trench isolations, carrying out a chemical etch until the silicon layer is exposed, and forming a FET by forming a channel, a source, and a drain of the field effect transistor in the silicon layer. |
申请公布号 |
US9275891(B2) |
申请公布日期 |
2016.03.01 |
申请号 |
US201313904194 |
申请日期 |
2013.05.29 |
申请人 |
Commissariat a l'energie atomique et aux energies alternatives;STMicroelectronics (Crolles 2) SAS |
发明人 |
Fenouillet-Beranger Claire;Denorme Stéphane |
分类号 |
H01L21/76;H01L21/762;H01L27/12;H01L21/84 |
主分类号 |
H01L21/76 |
代理机构 |
Occhiuti & Rohlicek LLP |
代理人 |
Occhiuti & Rohlicek LLP |
主权项 |
1. A process for fabricating an integrated circuit, said process comprising, in a stack of layers including a silicon substrate overlaid with a buried insulating layer overlaid with a silicon layer, etching first trenches into said silicon substrate, depositing a silicon nitride layer on said silicon layer so as to fill said first trenches and form first trench isolations, forming a mask on said silicon nitride layer, etching second trenches through said silicon nitride layer and into said silicon substrate, in a pattern defined by said mask, to a depth greater than a depth of said first trenches, filling said second trenches with an electrical insulator other than silicon nitride so as to form second trench isolations, carrying out a chemical etch until said silicon layer is exposed, and forming a field-effect transistor by forming a channel, a source, and a drain of said field effect transistor in said silicon layer. |
地址 |
Paris FR |