发明名称 Energy conservation in a multicore chip
摘要 Technologies are described herein for conserving energy in a multicore chip via selectively refreshing memory directory entries. Some described examples may refresh a dynamic random access memory (DRAM) that stores a cache coherence directory of a multicore chip. More particularly, a directory entry may be accessed in the cache coherence directory stored in the DRAM. Some further examples may identify a cache coherence state of a block associated with the directory entry. In some examples, refresh of the directory entry stored in the DRAM may be selectively disabled based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.
申请公布号 US9275696(B2) 申请公布日期 2016.03.01
申请号 US201213812967 申请日期 2012.07.26
申请人 EMPIRE TECHNOLOGY DEVELOPMENT LLC 发明人 Solihin Yan
分类号 G06F12/00;G11C7/10;G11C11/406;G06F12/08;G06F11/10 主分类号 G06F12/00
代理机构 Turk IP Law, LLC 代理人 Turk IP Law, LLC
主权项 1. A method to refresh a dynamic random access memory (DRAM) that stores a cache coherence directory of a multicore chip, the method comprising: accessing a directory entry in the cache coherence directory stored in the DRAM, the directory entry comprising a sharers item that identifies which of a plurality of cache memories in the multicore chip store a block associated with the directory entry, and an error correction code (ECC) for either or both detection and correction of an error in the sharers item; detecting the error in the sharers item based on the ECC; in response to a determination that the detected error is not correctable by use of the ECC: broadcasting a message to each cache memory of the plurality of cache memories in the multicore chip, wherein the message requests each cache memory to determine if the corresponding cache memory contains the block;receiving replies to the message; andupdating the sharers item to correct the detected error based on the received replies; identifying the cache coherence state of the block associated with the directory entry; and selectively disabling a refresh of the directory entry in the cache coherence directory stored in the DRAM based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.
地址 Wilmington DE US