| 发明名称 |
Memory banks with shared input/output circuitry |
| 摘要 |
A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The local bitlines of the outer memory banks connect to the local input/output logic via an upper metallization layer across regions of the inner memory banks. |
| 申请公布号 |
US9275686(B2) |
申请公布日期 |
2016.03.01 |
| 申请号 |
US201414288575 |
申请日期 |
2014.05.28 |
| 申请人 |
Avago Technologies General IP (Singapore) Pte. Ltd. |
发明人 |
Patel Manish Umedlal;Rai Dharmendra Kumar;Seikh Mohammed Rahim Chand |
| 分类号 |
G11C5/02;G11C7/06;G11C7/12;G11C15/00 |
主分类号 |
G11C5/02 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A Static Random Access Memory (SRAM) array, comprising:
a local input/output logic configured to access memory cells in memory banks, coupled with one or more global bitlines; inner memory banks disposed in either direction from the local input/output logic; outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic; and at least four local bitlines that run in a lower metallization layer of each of the memory banks; wherein local bitlines of the outer memory banks are rerouted vertically via an upper metallization layer over and across regions of the inner memory banks to connect to the local input/output logic. |
| 地址 |
Singapore SG |
