Fused booth encoder multiplexer

摘要

A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.

主权项

1. A fused Booth encoder multiplexer logic cell comprising:
a logic circuit having a plurality of operand input bits including multiplier input bits and multiplicand input bits, a dynamic node, a clock input, a logic tree containing a plurality of logic transistors, each logic transistor in said logic tree having a gate connected to one of the operand input bits and said logic transistors being interconnected to carry out a Boolean function according to a Booth encoding and selection algorithm to produce a partial product bit for a multiplication operation at the dynamic node in a single clock phase, a power transistor coupling said logic tree to a voltage source, said power transistor being controlled by said clock input, a foot transistor coupling said logic tree to electrical ground, said foot transistor being controlled by said clock input, and a latch connected to said dynamic node which maintains the partial product bit at an output node, said latch being controlled by said clock input, wherein said latch includes:
a first P-MOS transistor having a gate connected to said dynamic node, a source connected to said voltage source, and a drain;a second P-MOS transistor having a gate, a source connected to said voltage source, and a drain connected to said drain of said first P-MOS transistor;a first N-MOS transistor having a gate connected to said dynamic node, a source connected to said drains of said first and second P-MOS transistors, and a drain;a second N-MOS transistor having a gate connected to said clock input, a source connected to said drain of said first N-MOS transistor, and a drain connected to electrical ground;a third N-MOS transistor having a gate, a source connected to said drain of said first N-MOS transistor, and a drain connected to electrical ground; andan inverter having an input connected to said drains of said first and second P-MOS transistors, and an output connected to said gates of said first P-MOS transistor and said third N-MOS transistor, said inverter output being further connected to said output node to produce an inverted value;wherein said first P-MOS transistor and said first N-MOS transistor invert the value from the dynamic node, and the Boolean function of said logic tree accounts for inversion of the value by said first P-MOS transistor and said first N-MOS transistor.