| 主权项 |
1. A processor allowing to execute in parallel instructions from a single thread of instruction bundles, comprising:
an instruction memory comprising a plurality of instruction bundles comprising one or more instructions; a plurality of point-to-point communication means, hereafter called data communication links, wherein data can be stored, comprising
a write port wherein data can be written by performing a write operation and wherein information about write operation availability can be obtained, anda read port wherein data can be read following a predefined order in relation to the sequence of write operations previously performed on said write port by performing a read operation and wherein information about read operation availability can be obtained; and a plurality of processing means, hereafter called processing elements,
wherein a single instruction of said instruction bundle is executed by processing input data exclusively obtained from one or more said data communication link read ports and by writing the data produced by the execution exclusively to one or more said data communication link write ports,wherein said read ports providing said input data are selected based on instruction data,wherein said write ports where said result will be written are selected based on instruction data,wherein data stored in the data communication links can be explicitly managed by performing said read and write operations provided by said data communication links based on instruction data, wherein each instruction comprises
a field defining the operation to perform,a plurality of fields, one for each operand, each comprising first and second binary values, the first binary value defining the data communication link read port that will be selected by the processing element executing said instruction to obtain a corresponding operand, and the second binary value indicating if a read operation should be performed on the selected read port,a single field comprising a plurality of bits, one for each processor data communication link, wherein each bit defines whether the operation result should be written to the corresponding write ports of said data communication links, wherein data communications between instructions executed on said processing elements are only performed using said data communication links, wherein said instruction executions on said processing elements are synchronized based on read and write operation availability information provided by said data communication links, wherein there is one of said processing elements that is a branch unit providing an address of a next said instruction bundle to execute. |
