Multi processor and multi thread safe message queue with hardware assistance

摘要

A message exchange system for software components on different processors. A first component's attempt to load a write register with a message pointer (or a message itself) triggers a determination whether space exists in a shared memory queue. If so, the queue is updated by incrementing a message counter, writing the message/pointer into the queue where designated by a write pointer, and changing the write pointer to a next queue location. A second component's attempt to load the message/pointer from a read register triggers a determination whether there is at least one new message in the queue. If so, the queue is updated by decrementing the message counter, reading the message/pointer from the queue where designated by a read pointer, and changing the read pointer to point to a next queue location. The determinations and queue updates are performed atomically with respect to the software components.

主权项

1. A method of updating a message queue, said method comprising:
storing, in a message queue, a first message token associated with a first message, wherein said message queue is coupled to a first processor and a second processor; determining if there is sufficient space in said message queue for a second message token associated with a second message; if it is determined that sufficient space exists in said message queue for said second message token, updating said message queue by initiating a writing of said second message token into said message queue; and if it is determined that sufficient space does not exist in said message queue for said second message token, responsive to the determination that sufficient space does not exist in said message queue preparing to put a software component into a wait condition by copying a program counter into a temporary space, disabling interrupts and setting a program counter to a full handler sub-method wherein a hardware component disables said interrupts and a software component later enables said interrupts.