MEMORY ACCESS METHOD AND MEMORY SYSTEM

摘要

A first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, a first chip select signal, and a first higher-order address signal, and forwards a memory access instruction and a lower-order address signal received from a memory controller to the target second level buffer chip. The target second level buffer chip determines a target memory module according to a second chip select signal and a delayed address signal obtained by delays a second higher-order address signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. A cascading manner of a system memory is changed to a tree-like topological form, which avoids a protocol conversion problem, reduces the memory access time.

主权项

1. A memory access method, comprising:
sending, by a memory controller, a memory access instruction, a lower-order address signal, a first chip select signal, and a first higher-order address signal to a first level buffer chip, performing delay processing on a second higher-order address signal to obtain a delayed address signal, and sending the delayed address signal to a second level buffer chip, wherein:
the first level buffer chip is cascaded with the second level buffer chip,the second level buffer chip is connected to at least one memory module, wherein the memory module comprises at least one memory chip,the first chip select signal and the first higher-order address signal are used to identify a target second level buffer chip in the second level buffer chip, andthe lower-order address signal is used to identify a target memory chip in a target memory module; outputting, by the first level buffer chip, a second chip select signal to the second level buffer chip according to a preset mapping relationship, the first chip select signal, and the first higher-order address signal to gate the target second level buffer chip, and sending the memory access instruction and the lower-order address signal to the target second level buffer chip, wherein:
the second level buffer chip comprises at least one buffer chip, andthe target second level buffer chip is a buffer chip that is gated by using the second chip select signal and is in the second level buffer chip; determining, by the target second level buffer chip, the target memory module from the at least one memory module according to the delayed address signal and the second chip select signal, and determining the target memory chip from the target memory module according to the lower-order address signal, wherein the delayed address signal and the second chip select signal are used to identify the target memory module in the at least one memory module; and acquiring, by the target second level buffer chip, target data from the target memory chip according to the memory access instruction, and sending the target data to the memory controller by using the first level buffer chip.