Bootstrap MOS for High Voltage Applications

摘要

A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.

主权项

1. A device comprising:
a Junction Field-Effect Transistor (JFET) comprising:
a buried well region of a first conductivity type;a High-Voltage Well (HVW) region of the first conductivity type over the buried well region;a first well region of a second conductivity type opposite to the first conductivity type over the buried well region, wherein the first well region comprises an edge contacting an edge of the HVW region;a drain region of the first conductivity type in a surface portion of the HVW region;a first source region of the first conductivity type in a surface portion of the first well region; and a first gate electrode, with the first gate electrode and the drain region being on opposite sides of the first source region, wherein an on-current path of the JFET comprises:
a channel region directly underlying the first gate electrode; anda second portion in the buried well region.