| 发明名称 |
METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT |
| 摘要 |
A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced. |
| 申请公布号 |
US2016055286(A1) |
申请公布日期 |
2016.02.25 |
| 申请号 |
US201514820983 |
申请日期 |
2015.08.07 |
| 申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Baek Sang-hoon;Song Tae-joong;Oh Sang-kyu;Lee Seung-young |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method of designing a layout of an integrated chip (IC), the method comprising:
designing a first layout by placing and routing a plurality of standard cells that define the IC; and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns corresponding to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced. |
| 地址 |
Suwon-si KR |
