SEMICONDUCTOR DEVICE WITH SURROUNDING GATE TRANSISTORS IN A NOR CIRCUIT

摘要

A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NOR circuit. The NOR circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NOR circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NOR circuit.

主权项

1. A semiconductor device, comprising:
a plurality of transistors arranged in two rows and n columns on a substrate, where n≧2, to constitute a NOR circuit, each of the plurality of transistors having a source, a drain, and a gate arranged in layers in a direction perpendicular to the substrate, each of the plurality of transistors including:
a silicon pillar,an insulator that surrounds a side surface of the silicon pillar,a gate surrounding the insulator,a source region disposed on an upper portion or a lower portion of the silicon pillar, anda drain region disposed on an upper portion or a lower portion of the silicon pillar, the drain region being located on a side of the silicon pillar opposite to a side of the silicon pillar on which the source region is located; the plurality of transistors including:
n n-channel MOS transistors arranged in one row and n columns, andn p-channel MOS transistors arranged in one row and n columns, wherein the n n-channel MOS transistors and the n p-channel MOS transistors are arranged such that an n-channel MOS transistor in a k-th column and a p-channel MOS transistor in the k-th column form a pair, where k=1 to n, the gate of the n-channel MOS transistor in the k-th column and the gate of the p-channel MOS transistor in the k-th column being connected to one another, the drain regions of the n n-channel MOS transistors and the drain region of a p-channel MOS transistor in a first column are located on a side of the silicon pillars close to the substrate, the drain regions of the n n-channel MOS transistors and the drain region of the p-channel MOS transistor in the first column being connected to one another via a silicide region, and the source region of a p-channel MOS transistor in an s-th column and the drain region of a p-channel MOS transistor in an (s+1)-th column are connected to one another, where s=1 to n−1.