发明名称 |
PROCESSOR SYSTEM, ENGINE CONTROL SYSTEM AND CONTROL METHOD |
摘要 |
A processor system includes a master processor that successively processes a plurality of tasks, a checker processor that successively processes at least one of the plurality of tasks, and a control circuit that performs control so that the checker processor operates when the master processor and the checker processor perform a lock-step operation, and the checker processor stops its operation when the master processor and the checker processor do not perform the lock-step operation, the lock-step operation being an operation in which each of the master and checker processors processes the same task, in which the control circuit performs control so that a period from when a task is processed by the lock-step operation to when another task is processed in the next lock-step operation is equal to or shorter than a maximum test period, the maximum test period being a test period acceptable to the processor system. |
申请公布号 |
US2016055047(A1) |
申请公布日期 |
2016.02.25 |
申请号 |
US201514804970 |
申请日期 |
2015.07.21 |
申请人 |
Renesas Electronics Corporation |
发明人 |
Okamoto Tatsushi |
分类号 |
G06F11/07 |
主分类号 |
G06F11/07 |
代理机构 |
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代理人 |
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主权项 |
1. A processor system comprising:
a master processor that successively processes a plurality of tasks; a checker processor that successively processes at least one of the plurality of tasks; and a control circuit that performs control so that the checker processor operates when the master processor and the checker processor perform a lock-step operation, and the checker processor stops its operation when the master processor and the checker processor do not perform the lock-step operation, the lock-step operation being an operation in which each of the master processor and the checker processor processes the same task, wherein the control circuit performs control so that a period from when a task is processed by the lock-step operation to when another task is processed in the next lock-step operation is equal to or shorter than a maximum test period that is predetermined, the maximum test period being a test period acceptable to the processor system. |
地址 |
Kawasaki-shi JP |