Memory Controller for Heterogeneous Computer

摘要

A memory controller for heterogeneous computer processors dynamically adjusts access priorities by the different processors to maximize performance in the execution of a single parallel application program on both processor architectures. In one embodiment, the memory controller predicts sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences for improved implementation of the intended prioritization.

主权项

1. A computer for heterogeneous computing comprising:
a first processor having a first architecture; a second processor having a second architecture different from the first architecture; an electronic memory; a memory controller communicating memory access requests from the first and second processor to the memory, the memory controller giving a changing level of priority to memory access requests from the first processor according to a multivalue priority value; and a priority value adjuster measuring execution time of portions of a single parallel application on the first and second processor and adjusting the priority value to minimize a longest of the execution times of the portions during execution of the single parallel application.