DIRECT MEMORY BASED RING OSCILLATOR (DMRO) FOR ON-CHIP EVALUATION OF SRAM CELL DELAY AND STABILITY

摘要

A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an unmodified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures.

主权项

1. A method of measuring the delay from wordline input to bitline output of a static
random access memory (SRAM) cell, said method comprising: providing a plurality of delay stage circuits configured to form a ring oscillator, each said delay stage comprising an SRAM cell; guaranteeing an initial state of each delay stage circuit, wherein an incorrect state is corrected in a subsequent memory cycle; generating a falling edge in the output of each delay stage circuit in response to a rising edge of said wordline input; generating a rising edge in the output of each delay stage circuit in response to a falling edge of said wordline input; and measuring the frequency of said ring oscillator thereby evaluating the wordline to bitline delay of said SRAM cell.