Verification Of Photonic Integrated Circuits

摘要

Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.

主权项

1. One or more computer readable media storing computer-executable instructions for causing a computer to perform any of the new and nonobvious methods and method acts described herein, both alone and in combinations and subcombinations with one another.