| 发明名称 |
SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE |
| 摘要 |
Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs. |
| 申请公布号 |
US2016055922(A1) |
申请公布日期 |
2016.02.25 |
| 申请号 |
US201514813010 |
申请日期 |
2015.07.29 |
| 申请人 |
Intel Corporation |
发明人 |
Yang Joon-Sung;Kobla Darshan;Ju Liwei;Zimmerman David |
| 分类号 |
G11C29/00;G11C29/04 |
主分类号 |
G11C29/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory device comprising:
a memory stack having one or more memory die elements, including a first memory die element; and a system element coupled with the memory stack; wherein the first memory die element includes:
a plurality of through silicon vias (TSVs), the plurality of TSVs including a plurality of data TSVs and one or more spare TSVs, andself-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs. |
| 地址 |
Santa Clara CA US |
