LOW POWER DOUBLE PUMPED MULTI-PORT REGISTER FILE ARCHITECTURE

摘要

Embodiments that may allow for selectively tuning a delay of individual write paths within a memory are disclosed. The memory may comprise a memory array, a first data latch, a second data latch, and circuitry. The first and second data latches may be configured to each sample a respective data value, responsive to detecting a first edge of a first clock signal. The circuitry may be configured to detect the first edge of the first clock signal, and select an output of the first data latch responsive to detecting the first edge of the first clock signal. The circuitry may detect a subsequent opposite edge of the first clock signal, and select an output of the second data latch responsive to sampling the opposite edge of the first clock signal.

主权项

1. A memory, comprising:
a memory array; a first data latch configured to sample a first data value responsive to a first edge of a first clock signal, wherein the first data value is to be stored in the memory array; a second data latch configured to sample a second data value responsive to the first edge of the first clock signal, wherein the second data value is to be stored in the memory array; and circuitry configured to:
detect the first edge of the first clock signal;select an output of the first data latch responsive to detecting the first edge of the first clock signal;detect a subsequent opposite edge of the first clock signal;select an output of the second data latch responsive to detecting the subsequent opposite edge of the first clock signal;generate a second clock signal dependent upon the first clock signal, wherein a frequency of the second clock signal is twice a frequency of the first clock signal;generate a third clock signal dependent upon the first clock signal, wherein a frequency of the third clock signal is twice the frequency of the first clock signal, and wherein a duty cycle of the third clock signal is different than a duty cycle of the second clock signal; andselect one of the second clock signal and the third clock signal to generate a decoding clock signal, wherein the selection is dependent upon one or more operational parameters.