| 主权项 |
1. A delay apparatus, comprising:
a logic circuit that is connected between a first potential line and a first node and is driven by a driving current supplied from the first potential line; a driving current adjusting circuit that is connected in a current path through which the driving current flows between the first node and a second potential line and adjusts the driving current of the logic circuit; a supplying circuit that supplies a voltage or current to the first node; a measuring circuit that measures the voltage or current at the first node; and a controlling circuit that controls the voltage or current output from the supplying circuit based on the measured voltage or measured current at the first node measured by the measuring circuit, wherein the driving current adjusting circuit has: a plurality of memory elements that have a resistance that are connected in series with each other and changes in response to the voltage or current output from the supplying circuit. |
