SEMICONDUCTOR DEVICE AND FORMING METHOD

摘要

Disclosed is a semiconductor device that reduces the area of a transistor in a ReRAM. A plurality of memory cells differ from each other in the combination of bit line and plate line. The potential of plate line PL2 is a forming voltage. By contrast, the potentials of the other plate lines are +Vi. The potential of bit line BL2 is 0 V (ground potential). By contrast, the potentials of the other bit lines are +Vi. The potential of is +Vgf. By contrast, the potentials of the other word lines are +Vi.

主权项

1. A semiconductor device comprising:
a plurality of bit lines; a plurality of plate lines; and a plurality of memory cells that are electrically coupled respectively to one of the bit lines and to one of the plate lines and different from each other in the combination of the bit line and the plate line; wherein the memory cells each include: a variable resistance element; and a transistor having a gate electrode, the source of the transistor being electrically coupled to the bit line, the drain of the transistor being electrically coupled to the plate line through the variable resistance element, and wherein, in a situation where the variable resistance element in at least one of the memory cells is subjected to forming, the transistor in the memory cell breaks down between the drain and the source when the voltage between the plate line and the bit line is a forming voltage for the variable resistance element or breaks down between the drain and the gate when the voltage between the plate line and the gate electrode is the forming voltage.