发明名称 マルチコアプロセッサシステム、マルチコアプロセッサシステムの制御方法、およびマルチコアプロセッサシステムの制御プログラム
摘要 PROBLEM TO BE SOLVED: To reduce a load, and to improve the utilization efficiency of a processor.SOLUTION: When an exclusion start event is detected in an application A, a thread B is notified of an interruption signal (exclusion start). When the notification of the exclusion start event is received, the thread B is saved, and a slave CPU 102 is released. Since there is a thread Y in a thread queue, the thread Y is assigned to the slave CPU 102. Thus, the thread Y is executed in the slave CPU 102. When the thread Y is ended, the thread queue is empty, and a current power mode is shifted to a low power mode. Afterwards, when an exclusion end event is detected in the application A, the slave CPU 102 is notified of an interruption signal (exclusion end) from the application A. When the notification of the exclusion end event is received by the slave CPU 102, the thread B is restored to the slave CPU 102.
申请公布号 JP5867630(B2) 申请公布日期 2016.02.24
申请号 JP20150000562 申请日期 2015.01.05
申请人 富士通株式会社 发明人 山下 浩一郎;山内 宏真;宮▲崎▼ 清志
分类号 G06F9/50;G06F1/32;G06F9/48;G06F9/52 主分类号 G06F9/50
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