| 摘要 |
PURPOSE:To attain stable processing independently of the hardware and to improve the processing speed by using the hardware so as to execute the division on the expanded galois field. CONSTITUTION:A stage number smaller than number of terms of a division polynomial g(x) by one of multiplication processing units U0-Ue-1 are connected in cascade, and an EOR circuit E and m-set of delay latches R applying a delay of a unit time corresponding to the transmission period of one word are provided in response to the input vector of m-bit comprising the word of respective terms of an input polynomial f(x), respectively. The multiplication processing unit is equipped with a multiplication coefficient device KA and a vector being the result of multiplication of a coefficient (g) of a term corresponding to the division polynomial g(x) with an m-bit vector of an output polynomial Q(x) outputted from the division processing unit Ue is given to EOR circuits E1-Em, where exclusive OR is applied to each bit. The division processing unit Ue is provided with a division coefficient device Kv dividing the output vector of the output of the multiplication processing Ue-1 by the coefficient of the term of the highest order of the division polynomial g(x) and outputs sequentially the output of the division coefficient device as a quotient polynomial. |
