发明名称 |
Video processing apparatus |
摘要 |
According to one embodiment, a video processing apparatus includes a video data output device which outputs a data packet signal obtained by packetizing a data enable signal and a synchronization packet signal obtained by packetizing a synchronization signal, a transmission device which transmits the data packet signal and the synchronization packet signal, the data packet signal being delayed by a first delay amount and the synchronization packet signal being delayed by a second delay amount, and a timing controller which generates the data enable signal and the synchronization signal so as to set a pulse of the synchronization signal within a blanking period of the data enable signal based on the data packet signal and the synchronization packet signal. |
申请公布号 |
US9270869(B1) |
申请公布日期 |
2016.02.23 |
申请号 |
US201514644163 |
申请日期 |
2015.03.10 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Watanabe Manabu |
分类号 |
H04N5/06;H04N7/00;H04N5/067;G09G5/18;G09G5/00;G06T1/60 |
主分类号 |
H04N5/06 |
代理机构 |
White & Case LLP |
代理人 |
White & Case LLP |
主权项 |
1. A video processing apparatus comprising:
a video data output device which outputs a data packet signal obtained by packetizing a data enable signal and a synchronization packet signal obtained by packetizing a synchronization signal; a transmission device which transmits the data packet signal and the synchronization packet signal, the data packet signal being delayed by a first delay amount and the synchronization packet signal being delayed by a second delay amount different from the first delay amount; a timing controller which generates the data enable signal and the synchronization signal so as to set a pulse of the synchronization signal within a blanking period of the data enable signal based on the data packet signal and the synchronization packet signal; and a display device which displays a video based on the data enable signal and the synchronization signal generated by the timing controller. |
地址 |
Tokyo JP |