发明名称 |
Semiconductor integrated device for display drive |
摘要 |
In a display drive IC chip of an LCD or the like, an alignment mark is arranged in an alignment mark arrangement region on the main surface thereof, a dummy pattern is arranged on a lower layer, and an actual pattern is further arranged on the lower layer. |
申请公布号 |
US9269672(B2) |
申请公布日期 |
2016.02.23 |
申请号 |
US201414491995 |
申请日期 |
2014.09.20 |
申请人 |
Synaptics Display Devices GK |
发明人 |
Kumagai Yasuhiro;Koketsu Masami |
分类号 |
H01L23/544;H01L23/522 |
主分类号 |
H01L23/544 |
代理机构 |
Miles & Stockbridge P.C. |
代理人 |
Miles & Stockbridge P.C. ;King Eric G. |
主权项 |
1. A semiconductor integrated device for display drive comprising:
(a) a chip-shaped semiconductor substrate having a first main surface; (b) a large number of pad electrodes for bump electrode formation, provided on the first main surface side of the chip-shaped semiconductor substrate, which are constituted by a pad metal wiring layer; (c) an alignment mark arrangement region provided on the first main surface side of the chip-shaped semiconductor substrate; (d) an alignment mark, provided on the first main surface side of the chip-shaped semiconductor substrate and within the alignment mark arrangement region, which is constituted by the pad metal wiring layer; (e) an upper dummy wiring pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the alignment mark arrangement region, which is constituted by an upper metal wiring layer located below the pad metal wiring layer; and (f) an actual device pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the alignment mark arrangement region, which is constituted by a lower device layer located below the upper metal wiring layer, wherein the lower device layer comprises an element pattern contributing to a circuit configuration of the device. |
地址 |
Tokyo JP |