Latency computation circuitry

摘要

An integrated circuit may include multiple circuit blocks, each with an associated latency value. As an example, transceiver circuitry in an integrated circuit may receive different data packets and circuit blocks in the transceiver circuitry may have different latency values depending on the data packets received. The integrated circuit may further include latency computation circuitry that receives the different latency values from the multiple circuit blocks. The latency computation circuitry may accordingly output a total latency value for the multiple circuit blocks in the integrated circuit based on the received latency values.

主权项

1. An integrated circuit comprising:
a plurality of circuit blocks, wherein each circuit block in the plurality of circuit blocks exhibits a respective latency value; latency computation circuitry that includes a delay measurement circuit that is coupled to at least one circuit block of the plurality of circuit blocks and that measures the latency value of the at least one circuit block, wherein the latency computation circuitry outputs a total latency value for a portion of the plurality of circuit blocks based on the latency value measured by the delay measurement circuit; and timestamp generation circuitry that receives the total latency value from the latency computation circuitry and generates a timestamp according to the total latency value for each data packet that the plurality of circuit blocks receives and transmits.