Semiconductor devices having stressor regions and related fabrication methods

摘要

Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions.

主权项

1. A semiconductor device comprising:
a region of semiconductor material having a first conductivity type; an isolation region about the entire periphery of the region of semiconductor material, wherein the isolation region electrically insulates the region of semiconductor material; a stressor region formed in the region of semiconductor material and comprising a first stressor region; a first gate structure, a second gate structure, and a third gate structure formed overlying the region of semiconductor material, wherein the stressor region is disposed between the first gate structure and the second gate structure; a second stressor region formed in the region of semiconductor material between the second gate structure and the third gate structure; a first source/drain region having a second conductivity type formed in a first portion of the region of semiconductor material disposed between the first gate structure and the isolation region, the first source/drain region being adjacent to a channel region underlying the first gate structure; and a second source/drain region having the second conductivity type formed in the stressor region, the second source/drain region being adjacent to the channel region underlying the first gate structure; wherein the first gate structure, the second gate structure, and the third gate structure are in electrical communication with shared source/drain regions disposed therebetween.