Isolation switching for backup memory

摘要

Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.

主权项

1. A memory module comprising:
a host interface operable to be coupled to a host computer, the host interface including a standard dual inline memory module (DIMM) interface configured to be in electrical communication with the host computer using double data rate synchronous dynamic random-access memory (DDR SDRAM) data signals and DDR SDRAM address and control (addr/cont) signals; a circuit coupled to the host interface using a data bus and an addr/cont bus, the circuit configured to be in electrical communication with the host interface (i) using DDR SDRAM data signals by way of the data bus, and (ii) using DDR SDRAM addr/cont signals by way of the addr/cont bus; a volatile memory subsystem coupled to the circuit using a first data bus and a first addr/cont bus, the volatile memory subsystem including one or more DDR SDRAM memory elements, the volatile memory subsystem configured to be in electrical communication with the circuit (i) using DDR SDRAM data signals by way of the first data bus, and (ii) using DDR SDRAM addr/cont signals by way of the first addr/cont bus; a controller coupled to the circuit using a second data bus and a second addr/cont bus, the controller configured to be in electrical communication with the circuit (i) using DDR SDRAM data signals by way of the second data bus, and (ii) using DDR SDRAM addr/cont signals by way of the second addr/cont bus; and a non-volatile memory subsystem coupled to the controller, the non-volatile memory subsystem including one or more flash memory elements, the controller operable to manage the non-volatile memory subsystem, wherein, in response to signals from the controller, the circuit is operable to transfer data (i) between the host computer and the volatile memory subsystem by way of the data bus and the first data bus, and (ii) between the non-volatile memory subsystem and the volatile memory subsystem by way of the first data bus and the second data bus.