Shift register unit, gate driving circuit and display apparatus

摘要

A shift register unit, a gate driving circuit and a display apparatus are disclosed. The shift register unit includes a first TFT (T1) having a first electrode connected to an input terminal and a gate connected to a second clock signal input terminal; a second TFT (T2); a third TFT (T3) having a second electrode connected to an output terminal, a first electrode connected to a first clock signal input terminal, and a gate connected to the second electrode of the first TFT; a fourth TFT (T4); a fifth TFT (T5) having a gate connected to the second clock signal input terminal, a first electrode connected to the output terminal and a second electrode connected to the low potential connecting terminal; a capacitor (C1), and thus the burrs and miscellaneous spikes in a gate driving waveform outputted by the circuit can be suppressed well.

主权项

1. A shift register unit including an input terminal, an output terminal, a first clock signal input terminal, a second clock signal input terminal, a low potential connecting terminal and a reset terminal, the shift register unit further consisting of:
a first Thin Film Transistor TFT having a first electrode connected to the input terminal and a gate connected to the second clock signal input terminal; a second TFT having a first electrode connected to the second electrode of the first TFT, a gate connected to the reset terminal, and a second electrode connected to the low potential connecting terminal; a third TFT having a second electrode connected to the output terminal, a first electrode connected to the first clock signal input terminal, and a gate connected to a second electrode of the first TFT; a fourth TFT having a first electrode connected to the output terminal, a gate connected to the reset terminal, and a second electrode connected to the low potential connecting terminal; a fifth TFT having a gate directly connected to the second clock signal input terminal, a first electrode directly connected to the output terminal, and a second electrode connected to the low potential connecting terminal; and a capacitor connected between the gate and the second electrode of the third TFT; wherein a first clock signal input from the first clock signal input terminal and a second clock signal input from the second clock signal input terminal have a same period and are inverted to each other.