Using stress reduction barrier sub-layers in a semiconductor die

摘要

A semiconductor die, which includes a substrate, a group of primary conduction sub-layers, and a group of separation sub-layers, is disclosed. The group of primary conduction sub-layers is over the substrate. Each adjacent pair of the group of primary conduction sub-layers is separated by at least one of the group of separation sub-layers. As a result, the group of separation sub-layers mitigates grain growth in the group of primary conduction sub-layers.

主权项

1. A semiconductor die comprising:
a substrate; a metallization layer on the substrate; a first plurality of primary conduction sub-layers over the substrate; a first plurality of separation sub-layers, wherein: at least a corresponding one of the first plurality of separation sub-layers is disposed between each adjacent pair of the first plurality of primary conduction sub-layers; and the first plurality of separation sub-layers is adapted to mitigate grain growth in the first plurality of primary conduction sub-layers and the first plurality of primary conduction sub-layers and the first plurality of separation sub-layers provide a first multiple sub-layer metallization layer on the substrate, wherein the first multiple sub-layer metallization layer is on the metallization layer; a plurality of epitaxial layers on the metallization layer; a via that has a portion that is perpendicular to two of the plurality of epitaxial layers, where a portion of the metallization layer along the via traverses between the two of the plurality of epitaxial layers; and a via membrane on the via where the via membrane comprises a portion of the first multiple sub-layer metallization layer.