Gate recessed FDSOI transistor with sandwich of active and etch control layers

摘要

The structure and the fabrication methods herein implement a fully depleted, recessed gate silicon-on-insulator (SOI) transistor with reduced access resistance, reduced on-current variability, and strain-increased performance. This transistor is based on an SOI substrate that has an epitaxially grown sandwich of SiGe and Si layers that are incorporated in the sources and drains of the transistors. Assuming a metal gate last complementary metal-oxide semiconductor (CMOS) technology and using the sidewall spacers as a hard mask, a recess under the sacrificial gate reaching all the way through the SiGe layer is created, and the high-K gate stack and metal gate are formed within that recess. The remaining Si region, having a precisely controlled thickness, is the fully depleted channel.

主权项

1. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising:
a fully depleted semiconductor on insulator (FDSOI) substrate having a first semiconductor layer on a second semiconductor layer that is on an insulator layer, which insulator layer is on an underlying substrate, wherein the second semiconductor layer is a silicon layer and the first semiconductor layer is a silicon-germanium layer, or wherein the second semiconductor layer is a silicon-germanium layer and the first layer is a silicon layer; a source region and a drain region formed in the second semiconductor layer having a second dopant level implant establishing a second dopant concentration in the source and drain regions formed in the second semiconductor layer; and a source region and a drain region formed in the first semiconductor layer having a first dopant level implant establishing a first dopant concentration in the source and drain regions formed in the first semiconductor layer; a semiconductor channel region in the second semiconductor region separating the source and the drain regions; the second semiconductor layer having a thickness for fully depleted operation and wherein the semiconductor channel region extending through the second semiconductor layer to the insulator layer; a silicide layer formed over at least a portion of the source region formed in the first semiconductor layer and a silicide layer formed over the drain region formed in the first semiconductor layer; a gate dielectric over the semiconductor channel region; and, a conductive gate region over the gate dielectric, the gate dielectric also separating the conductive gate from the first semiconductor layer adjacent the conductive gate; wherein a cross-section of a MOSFET of a first conductivity type and a cross-section of a MOSFET of a second conductivity type may have the same cross-section, layer for layer, other than the conductivity types and possible reversal of the position of the silicon and the silicon-germanium layers.