Dual-port positive level sensitive reset data retention latch

摘要

In an embodiment of the invention, a dual-port positive level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

主权项

1. A dual-port positive level sensitive reset data retention latch comprising:
a clocked inverter configured to receive a first data bit, a first clock signal, a second clock signal, a reset control signal and a retention mode control signal (RET) wherein the first clock signal, the second clock signal, the reset control signal and the retention mode control signal determine whether a first data output from the clocked inverter is the binary compliment of the first data bit or an indeterminate value; a dual-port latch configured to receive the first data output of the clocked inverter, a second data bit, the first clock signal, the second clock signal, the reset control signal, the retention mode control signal, a first latch control signal and a second latch control signal wherein the first clock signal, the second clock signal, the reset control signal, the retention mode control signal, the first latch control signal and the second latch control signal determine whether the first data output of the clocked inverter or the second data bit is latched in the dual-port latch.