| 发明名称 | Semiconductor chips and semiconductor systems for executing a test mode | ||
| 摘要 | Semiconductor chips are provided. The semiconductor chip includes a selection phase clock generator and a data input/output portion. The selection phase clock generator is configured to receive an external clock signal and an inversed external clock signal to generate phase clock signals, configured to receive a first external test clock signal and a second external test clock signal to generate test phase clock signals, and configured to output the phase clock signals or the test phase clock signals as selection phase clock signals in response to a test mode signal. | ||
| 申请公布号 | US9270285(B2) | 申请公布日期 | 2016.02.23 |
| 申请号 | US201313944345 | 申请日期 | 2013.07.17 |
| 申请人 | SK Hynix Inc. | 发明人 | Kang Tae Wook;Na Kwang Jin |
| 分类号 | G11C8/00;H03L7/08;G11C7/22;G11C29/12 | 主分类号 | G11C8/00 |
| 代理机构 | William Park & Associates Ltd. | 代理人 | William Park & Associates Ltd. |
| 主权项 | 1. A semiconductor chip comprising: a selection phase clock generator configured to receive an external clock signal and an inversed external clock signal to generate phase clock signals, configured to receive a first external test clock signal and a second external test clock signal in response to a reference voltage having a constant level to generate test phase clock signals, and configured to output the phase clock signals or the test phase clock signals as selection phase clock signals in response to a test mode signal; and a data input/output portion configured to receive and output data in synchronization with the selection phase clock signals. | ||
| 地址 | Gyeonggi-do KR | ||