Semiconductor memory device and semiconductor system including the same

摘要

Disclosed herein is a semiconductor memory device using a pre-fetch method and a semiconductor system including the same. The semiconductor memory device may include a memory bank having an odd-numbered array region suitable for inputting/outputting data through N first local lines in response to an odd-numbered column address, and an even-numbered array region suitable for inputting/outputting data through N second local lines in response to an even-numbered column address, N being a positive integer, a column address generation unit suitable for consecutively generating the odd-numbered column address and the even-numbered column address whose generation sequence is controlled depending on whether an external column address has an even-numbered value or an odd-numbered value, and N global lines coupled in common to the N first local lines and the N second local lines, suitable for inputting/outputting data.

主权项

1. A semiconductor memory device comprising:
a memory bank having an odd-numbered array region suitable for inputting/outputting data through N first local lines in response to an odd-numbered column address, and an even-numbered array region suitable for inputting/outputting data through N second local lines in response to an even-numbered column address, N being a positive integer; a column address generation unit suitable for consecutively generating the odd-numbered column address and the even-numbered column address in response to whether an external column address has an even-numbered value or an odd-numbered value; and N global lines coupled in common to the N first local lines and the N second local lines, suitable for inputting/outputting data, wherein the column address generation unit includes:
a column address decoding unit suitable for generating an internal column address by decoding the external column address; anda column address output unit suitable for outputting the internal column address as the even-numbered or odd-numbered column address, inverting a least significant bit (LSB) of the internal column address, and outputting the inverted column address as the odd-numbered column address or the even-numbered column address.