发明名称 Semiconductor memory device
摘要 A semiconductor memory device includes a first set of memory cells commonly connected to a first word line, a second set of memory cells commonly connected to a second word line, and a control circuit configured to execute a writing operation on the memory cells, including controlling voltages applied to the first and second word lines. The writing operation includes a coarse program operation and a fine program operation and the control circuit executes the writing operation on the first and second sets of memory cells in a single write operation that includes starting the following operations in order: (1) the coarse program operation on the first set of memory cells; (2) the coarse program operation on the second set of memory cells; (3) the fine program operation on the first set of memory cells; and (4) the fine program operation on the second set of memory cells.
申请公布号 US9269445(B1) 申请公布日期 2016.02.23
申请号 US201514634873 申请日期 2015.03.01
申请人 Kabushiki Kaisha Toshiba 发明人 Abe Kenichi;Shirakawa Masanobu
分类号 G11C11/34;G11C16/04;G11C16/10 主分类号 G11C11/34
代理机构 Patterson & Sheridan, LLP 代理人 Patterson & Sheridan, LLP
主权项 1. A semiconductor memory device comprising: a memory cell array including a first set of memory cells commonly connected to a first word line, and a second set of memory cells commonly connected to a second word line; and a control circuit configured to execute a writing operation on the memory cells, including controlling voltages applied to the first and second word lines, wherein the writing operation includes a coarse program operation and a fine program operation and the control circuit executes the writing operation on the first and second sets of memory cells in a single write operation that includes starting the following operations in order: (1) the coarse program operation on the first set of memory cells; (2) the coarse program operation on the second set of memory cells; (3) the fine program operation on the first set of memory cells; and (4) the fine program operation on the second set of memory cells.
地址 Tokyo JP