Sharing memory using processor wait states

摘要

Apparatus having corresponding methods and computer-readable media comprise: a memory having a plurality of ports; a plurality of processors, wherein each processor is configured to access a respective port of the memory, and wherein each processor is configured to wait responsive to assertion of a respective wait signal; and an arbiter configured to assert the wait signals responsive to memory enable signals asserted by the processors such that the memory is accessed by only one of the processors at a time.

主权项

1. An apparatus comprising:
a memory having a plurality of ports; a plurality of processors, wherein each processor is configured to access a respective port of the memory, and wherein each processor is configured to wait responsive to assertion of a respective wait signal; and an arbiter configured to:
in response to a first one of the plurality of processors asserting a first one of memory enable signals when a turn signal is in a first state:
assert a first one of the wait signals for a second one of the plurality of processors;allow the first one of the plurality of processors to access the memory; andtransition the turn signal from the first state to a second state; andin response to the second one of the plurality of processors asserting a second one of the memory enable signals when the turn signal is in the second state:
assert a second one of the wait signals for the first one of the plurality of processors;allow the second one of the plurality of processors to access the memory; andtransition the turn signal from the second state to one of (i) the first state and (ii) a third state.