发明名称 Application scheduling in heterogeneous multiprocessor computing platform based on a ratio of predicted performance of processor cores
摘要 Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.
申请公布号 US9268611(B2) 申请公布日期 2016.02.23
申请号 US201012890653 申请日期 2010.09.25
申请人 Intel Corporation 发明人 Iyer Ravishankar;Srinivasan Sadagopan;Zhao Li;Illikkal Rameshkumar G.
分类号 G06F9/50;G06F11/34;G06F12/08 主分类号 G06F9/50
代理机构 Mnemoglyphics, LLC 代理人 Mnemoglyphics, LLC ;Mennemeier Lawrence M.
主权项 1. A processor with application scheduling using performance-based core modeling prediction heuristics comprising: a storage unit to store a performance history table (PHT), said PHT including performance statistics, and one or more performance counters, said performance counters corresponding to performance of an application having been executed on one or more of a plurality of heterogeneous processor cores of the processor; and logic to determine whether a first processor core of the plurality of processor cores is to execute the application based, at least in part, on a ratio of predicted performance of the application if it were executed on the first processor core versus on another processor core of the plurality of processor cores, the performance to be predicted for the first processor core from the one or more performance counters of said another processor core, and to cause scheduling of the application for execution on the first processor core whenever said ratio of predicted performance on the first processor core versus said another processor core indicates either one of the larger performance gains or one the smaller performance losses, wherein said ratio of predicted performance is predicted from an issue width ratio on the first processor core versus said another processor core as diminished by one or more predicted stall factor ratios, and wherein the logic is to transmit data to an operating system to cause scheduling of the application on the first processor core.
地址 Santa Clara CA US