SUB-BLOCK ERASE

摘要

Provided is a method for operating a NAND array which includes a plurality of blocks of memory cells. One block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings share a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including one or more members of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset. Tunneling is inhibited in memory cells coupled to an unselected subset including one or more members of the set of word lines.